A DLL (Delay Locked Loop) circuit is used as an interface or the like of a memory, such as a DDR (Double Data Rate) memory, to/from which data is writable/readable in synchronization with a clock signal. The DLL circuit utilizes a PLL (Phase Locked Loop) function to adjust the delay time (output delay) before an inputted signal is outputted. Specifically, the DLL circuit compares an externally supplied reference clock signal and a clock signal generated in an internal voltage-controlled oscillation circuit to control the oscillation frequency of the clock signal, and adjusts the delay time by using a signal relating to this control.
However, a semiconductor device such as the DLL circuit generally has only one voltage-controlled oscillation circuit. Therefore, a range of the oscillation frequency of the clock signal internally generatable has been conventionally limited, and a range of the reference clock signal usable in the DLL circuit has been also limited.
One solution to such a problem was a voltage-controlled oscillation circuit which has a selector in a ring oscillation circuit (an inverter chain constituted of cascaded inverter circuits) included in the voltage-controlled oscillation circuit, thereby allowing the control for changing the number of stages (see, for example, Japanese Patent Application Laid-open No. Hei 5-343956 (Patent document 1)).
As a conventional voltage-controlled oscillation circuit, there is one structured such that a capacitor with one end thereof grounded is connectable to an output of an inverter circuit in a ring oscillation circuit as required to increase load capacitance at the output of the inverter circuit, thereby allowing the adjustment of the oscillation frequency (see, for example, Japanese Patent Application Laid-open No. Hei 8-102643 (Patent document 2)).
In the voltage-controlled oscillation circuit described in Japanese Patent Application Laid-open No. Hei 5-343956, however, the selector for controlling the number of stages is in a loop of the ring oscillation circuit. This has posed a problem that a duty ratio of the generated clock signal, which should be 5:5 as shown in FIG. 9A and FIG. 9B, may possibly become improper as shown in FIG. 9C and FIG. 9D. The improper duty ratio of the generated clock signal may possibly cause a great trouble under a high-speed operation as shown especially in FIG. 9D. If it is used in, for example, the DLL circuit, the adjustment of the delay time may possibly become unfeasible under the high-speed operation.
Further, the voltage-controlled oscillation circuit in which the capacitor with one end thereof grounded is connectable to the output of the inverter circuit in the ring oscillation circuit as required to thereby allow the adjustment of the oscillation frequency has problems, which will be described below with reference to FIG. 10A and FIG. 10B.
In FIG. 10A, an inverter circuit I101 connected to a power supply line Vdd and a ground line Vss inverts an input signal Vin inputted thereto to output it to an output node Va. Further, a capacitor C2 with one end thereof grounded is connected at the other end to an output of the inverter circuit I101, via a transistor T101 whose gate is supplied with a control signal VCont. The control signal VCont ON/OFF controls the transistor T101 to control the load capacitance at the output of the inverter circuit I101. Here, as shown in FIG. 10B, in the transistor T101, there exist parasitic capacitors Ca, Cb whose capacitances are basically large since these capacitors are bulk capacitors. In FIG. 10B, 102 denotes a drain, 103 a source, and 104 a gate.
Therefore, in the voltage-controlled oscillation circuit in which the capacitor with the one end thereof grounded is connectable to the output of the inverter circuit in the ring oscillation circuit as required, the bulk capacitance Ca is loaded on the output of the inverter circuit I101 when the transistor T101 is off, while the bulk capacitances Ca, Cb in addition to the capacitance C2 are loaded thereon when the transistor T101 is on. Since the bulk capacitors Ca, Cb are basically large in capacitance as described above, the control of a small oscillation frequency, namely, delicate adjustment of the delay time is not feasible.
Patent Document 1
Japanese Patent Application Laid-open No. Hei 5-343956
Patent Document 2
Japanese Patent Application Laid-open No. Hei 8-102643